Synopsys is a global leader in electronic design automation. We play a role in accelerating technology around the world, as well as the culture of solid growth, professionalism and integrity the company offers in what is still startup, teamwork atmosphere. From engineering to programming, design, R&D and support, Synopsys provides unparalleled opportunity to learn, grow and be on the cutting-edge of technology.
You will be a member of the R&D team developing a software product called ESP that performs sequential equivalence checking verification of custom IC designs, with a particular focus on embedded memories and standard cell libraries modeled at behavior or RTL Verilog or SPICE netlist levels. The verification engine is based on symbolic simulation technologies, and makes heavy use of Binary Decision Diagrams (BDDs), among other formal techniques.
• Enhance the product through algorithm development and code implementation.
• Learn, analyze, test, debug, and maintain the existing ESP code base.
• Interact with other members of Synopsys R&D, customer support, and sales experts as necessary to understand customer needs and product goals.
• BS/MS in CS/EE/Math/Physics or a related field, with 2+ years of work experience developing software products.
• C/C++/STL programming, with knowledge of object-oriented design.
• Broad understanding of data structures, algorithms, heuristics, and their application.
• Good analytical and problem-solving skills.
• Exercise of judgment in developing methods, techniques, and evaluation criteria to meet project goals. Comfortable with learning and applying new technologies.
• Ability to work in both independent and collaborative settings.
• Good written and oral communication skills in English.
Optional Skills Desired:
• Familiarity with Unix and associated software development tools (Perforce, Coverity, gcov, Valgrind)
• Knowledge of software specification, design process, and regression testing.
• Special consideration given to those with background and experience in: formal verification; logic and/or symbolic simulation; SPICE-level design analysis; BDD and SAT technology.